Seminars

CANCELLED: The Coming Age of Physical Synthesis

Dr. Zhuo Li - IBM Austin Research Labs
Wednesday, October 28, 2009, 3:00 pm, Engineering 2 Building, Room 280

 

Electric: a Multi-Threaded Integrated Circuit System

Dr. Steven M. Rubin - Sun Microsystems
Thursday, June 4, 2009, 6:00 pm, Engineering 2 Building, Room 180

 

IEEE Region 6 Central Meeting Keynote: PG&E SmartGrid

Chris Knudsen - Director of the Technology Innovation Center at PG&E
Saturday, March 28, 2009, 1:00 pm, UCSC E2 Simularium

 
VLSI Design and Automation Group @ UC Santa Cruz

 

Welcome to the UC Santa Cruz VLSI Design Automation (VLSI-DA) group web page. VLSI-DA was founded at UC Santa Cruz in the Department of Computer Engineering in Fall 2006. It is currently a small, but fast growing group. The primary research focus of the group is on physical circuit design. Often, this involves writing Computer-Aided Design (CAD) tools for large-scale circuit optimization. Topics being investigated include design for variability and reliability, thermal-aware design, and error tolerant circuit design.

If you are interested in learning more about our group, please do not hesitate to contact me. Potential students should look at the "How to Join" section on the left.

 
Copyright © 2009 VLSI Design and Automation Group. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.
 

Latest News

Prof. Guthaus chairs ACM/SIGDA CADathlon at ICCAD

Prof. Guthaus chaired the 8th annual CADathlon programming contest at ICCAD on Nov. 1, 2009.

 
UCSC, IFIP and VLSI-SoC 2012

Prof. Guthaus was elected as a member of the IFIP Working Group 10.5. Prof. Guthaus was nominated to prepare a proposal to host the flagship conference, the IFIP/IEEE VLSI-SoC, in Santa Cruz in 2012. Future dates currently include Florianopolis, Brazil in 2009; Madrid, Spain in 2010; and Hong Kong, China in 2011.

 
NASA Aligned Research Program Grant

The VLSI-DA group received $43k in funding for the 2009-2010 academic year from the NASA Aligned Research Program (ARP) for Radiation Hard FPGA Synthesis.