News

  • Monday, November 25, 2019

    Google has provided a generous gift to support the OpenRAM memory compiler. This gift will be used for improved coordination with other open-source projects, improved process support, and other general improvements.

  • Tuesday, November 19, 2019

    Hunter Nichols presented his open-source PUF analysis tool -- Puffery. Prof. Guthaus was on the panel discussing gaps in EDA technology. 

  • Tuesday, June 18, 2019

    Two papers from the group were accepted into the VLSI-SOC to be held in Cuzco, Peru on October 6-9, 2019. The first was accepted as a long, oral presentation on Automated Synthesis of Multi-Port Memories and Control by Hunter Nichols, Michael Grimes, Jennifer Sowash, Jesse Cirimelli-Low and Matthew Guthaus. The second was accepted as a short, poster presentation on Bottom Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization by Bin Wu and Matthew Guthaus.

  • Tuesday, June 4, 2019

    Prof. Guthaus presented on OpenRAM Multiport Memory IP at the Design Automation Conference Designer/IP Forum. The authors of the presentation are Matthew R. Guthaus, Hunter Nichols, Michael Grimes, Jesse L. Cirimelli-Low, and Jennifer Sowash.

  • Wednesday, April 17, 2019

    The OpenRAM talk at the Free Silicon Conference is now available online. Numerous other talks on open-source hardware and CAD are available at:
    https://peertube.f-si.org/video-channels/fsic2019/videos

     

  • Tuesday, April 2, 2019

    Prof. Guthaus presented a talk on OpenRAM: Enabling Memory Research at the Cadence CDNLive conference in Santa Clara on April 2-3, 2019. 

  • Wednesday, January 23, 2019

    Professor Guthaus will be presenting on OpenRAM at the Free Silicon Conference (FSiC) at Sorbonne University in Paris, March 13-16, 2019.  

  • Monday, January 14, 2019

    A major release of OpenRAM is now available. This contains multi-port support, power supply improvements, improved abstractions, and many bug fixes. Please check it out at: https://vlsida.github.io/OpenRAM/ 

  • Thursday, August 16, 2018

    Prof. Riadul Islam and Prof. Guthaus have had another journal paper from his PhD thesis accepted into the IEEE Transactions on Circuits and Systems I. The article is on HCDN: Hybrid-Mode Clock Distribution Networks.

  • Wednesday, June 27, 2018

    We presented a poster at the Design Automation Conference on hybrid current-mode clocks. The first hybrid-mode clock synthesis methodology improves clock jitter-induced delay variation and saved 42-45% average power with similar skew on industrial benchmarks.

  • Monday, May 14, 2018

    Prof. Riadul Islam and Prof. Guthaus have had another journal paper from his PhD thesis accepted into the IEEE Transactions on Very Large Scale Integration Systems. The article is on DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis.

  • Friday, September 1, 2017
  • Monday, May 22, 2017

    Dr. Riadul Islam successfully defended his thesis on Current-Mode Clocking And Synthesis Considering Low-Power And Skew.

  • Monday, March 6, 2017

    Reducing Variability in Subthreshold Circuits

    Reduced form-factor in portable electronics has made energy-efficiency the primary target. Subthreshold operation is a low-power technique delivering significant energy efficiency. However, circuits in subthreshold are very sensitive to process vari- ation. Utilizing subthreshold operation and leveraging energy efficiency necessitates compensation techniques to mitigate process variation.

    This work focuses on subthreshold operation in Field Programmable Gate Arrays (FPGAs) and determines the components influencing circuit energy-efficiency.  Mitigating the impact of threshold voltage variation using body bias technique is stud- ied. Using this, a methodology to mitigate the impact of threshold voltage variation in standard cells is developed. With the support of CAD tools this methodology can be extended to FPGAs.

    The specific contributions of this thesis are: design and implementation of a subthreshold FPGA chip using body bias as a compensation mechanism against thresh- old voltage variation. analysis of performance and energy of a subthreshold FPGA using a high-level characterization framework. Using this framework the minimum energy point of the subthreshold FPGA was found to be in deep subthreshold, and a performance window of 30X with a 2X energy range was identified. A design methodology to mitigate threshold voltage variation by delivering optimized and adaptive body bias in circuits with standard cells. Using two algorithms, this methodology produces standby energy savings of upto 21.06% on average and active energy savings of upto 9.62% on average.

  • Wednesday, February 8, 2017

    PhD candidate Raj Sankaranarayanan had a paper on Energy Savings and Performance Improvement in Subthreshold Using Adaptive Body Bias that accepted into the Great Lakes Symposium on VLSI. 

  • Monday, November 7, 2016

    The VLSI-DA group along with collaborators at Oklahoma State University have released the OpenRAM open source memory compiler projetc on GitHub. The work was presented at ICCAD in the paper, OpenRAM: An open-source memory compiler.

  • Sunday, October 2, 2016

    Prof. Guthaus along with collaborators at Oklahoma State University have published the first paper using OpenRAM. The paper is A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS.

  • Thursday, September 15, 2016

    PhD candidate Riadul Islam's paper on CMCS: Current-Mode Clock Synthesis was accepted into the Transactions on VLSI. 

  • Wednesday, March 30, 2016

    MS student Jie Zhang graduated after finishing his MS thesis. His project was the SlugHeart mobile EKG device along with an Android app. This allows low-power EKG analysis for a variety of future projects. Jie is now a software engineer at Yodlee, Inc. (recently acquired by Envestnet).

  • Tuesday, January 27, 2015

    PhD student Riadul Islam had his journal article titled "Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop" accepted for publication in the IEEE Transactions on Circuits and Systems I. Great work!

  • Thursday, January 8, 2015

    The VLSI DA group has had three papers accepted for presentation at the 2015 International Symposium on Circuits and Systems (ISCAS) in Lisbon, Portugal. The articles are:

    • P.-Y. Lin, H. Fahmy, R. Islam, M. R. Guthaus, ``LC Resonant Clock Resource Minimization using Compensation Capacitance''
    • H. Fahmy, P.-Y. Lin, R. Islam, M. R. Guthaus, ``Switched Capacitor Quasi-Adiabatic Clocks''
    • B. Lacara, P.-Y. Lin, M. R. Guthaus, ``Multi-Frequency Resonant Clocks''

    The first two papers are the initial PhD work by Ping-Yao and Hany while the third paper is the final results of Ben's Master's thesis. Congratulations!

     

  • Sunday, September 28, 2014

    Rebecca Rashkin and Jie Zhang have joined the VLSI DA group to work on new medical and wearable sensor systems. Rebecca is pursuing her PhD while Jie is pursuing an MS in Computer Engineering. Welcome!

  • Friday, March 7, 2014

    Prof. Guthaus has received two seed grants for a new direction of low-power medical devices research. One seed grant is from the Baskin School of Engineering while another is from CITRIS. These grants are in collaboration with UCSF and UCD Medical Centers. Prof. Guthaus has been on sabbatical for much of the 2013-2014 academic year at UCSF Medical Center.

     

     

  • Saturday, January 25, 2014

    As the first part of his thesis research, Riadul Islam had his paper on "Current-Mode Clock Distribution" accepted as a full paper and presentation at the International Symposium on Circuits and Systems (ISCAS) 2014 in Melbourne, Australia.

  • Wednesday, October 9, 2013

    Power consumption is the predominant challenge in modern
    high-performance systems and is becoming increasingly important due to
    mobile applications. High power consumption leads to decreased battery
    lifetime, cooling challenges which limit form factors, and large on-chip
    temperatures which can decrease reliability. While stand-by and idle
    power can be minimized with many techniques, active-mode dynamic
    power consumption during peak operation continues to be a formidable
    barrier. Reducing the clock power consumption can significantly reduce
    overall active-mode dynamic power. This embedded tutorial explores the
    recent commercial and academic results in the design and optimization
    of distributed-LC resonant clocks and discusses the future challenges and
    open research problems.

    The paper can be found here.

Pages

News

  • Google has provided a generous gift to support the OpenRAM memory compiler. This gift will be used for improved coordination with other open-source projects, improved process support, and other general improvements.

  • Hunter Nichols presented his open-source PUF analysis tool -- Puffery. Prof. Guthaus was on the panel discussing gaps in EDA technology. 

  • Two papers from the group were accepted into the VLSI-SOC to be held in Cuzco, Peru on October 6-9, 2019. The first was accepted as a long, oral presentation on Automated Synthesis of Multi-Port Memories and Control by Hunter Nichols, Michael Grimes, Jennifer Sowash, Jesse Cirimelli-Low and Matthew Guthaus. The second was accepted as a short, poster presentation on Bottom Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization by Bin Wu and Matthew Guthaus.

  • Prof. Guthaus presented on OpenRAM Multiport Memory IP at the Design Automation Conference Designer/IP Forum. The authors of the presentation are Matthew R. Guthaus, Hunter Nichols, Michael Grimes, Jesse L. Cirimelli-Low, and Jennifer Sowash.