News

  • Saturday, January 25, 2014

    As the first part of his thesis research, Riadul Islam had his paper on "Current-Mode Clock Distribution" accepted as a full paper and presentation at the International Symposium on Circuits and Systems (ISCAS) 2014 in Melbourne, Australia.

  • Wednesday, October 9, 2013

    Power consumption is the predominant challenge in modern
    high-performance systems and is becoming increasingly important due to
    mobile applications. High power consumption leads to decreased battery
    lifetime, cooling challenges which limit form factors, and large on-chip
    temperatures which can decrease reliability. While stand-by and idle
    power can be minimized with many techniques, active-mode dynamic
    power consumption during peak operation continues to be a formidable
    barrier. Reducing the clock power consumption can significantly reduce
    overall active-mode dynamic power. This embedded tutorial explores the
    recent commercial and academic results in the design and optimization
    of distributed-LC resonant clocks and discusses the future challenges and
    open research problems.

    The paper can be found here.

  • Thursday, May 23, 2013

    As the final part of his thesis research, Dr. Sheldon Logan had two papers accepted at the 2013 Midwest Symposium on Circuits and Systems (MWSCAS). The two papers were on "Redundant C4 Power Pin Placement to Ensure Robust Power Grid Delivery" and "A Decap Placement Methodology for Reducing Joule Heating and Temperature in PSN Interconnect."

  • Monday, April 15, 2013

    Dr. Sheldon Logan successfully defended his PhD thesis on Thermal-Aware CAD for Modern Integrated Circuits. 

    Power density in modern integrated circuits (ICs) continues to increase at an alarming rate. In turn, larger power densities result in higher peak temperatures which can reduce chip reliability and further increase leakage power consumption. Thermal-aware CAD design is a method to combat these problems. However most existing thermal-aware CAD research has focused on thermal-aware floorplanning and placement. These thermal-aware floorplanners have several problems such as long execution times and being limited to only one method of reducing peak temperatures. In addition most thermal-aware CAD research has only focused on reducing chip peak temperatures and not other reliability concerns such as high interconnect temperatures, wire/C4 bump electromigration, and thermal-cyclic C4
    bump failure.
     
    This thesis proposes several new algorithms and methodologies that can be used
    to directly reduce high on chip temperatures and mitigate the reliability concerns caused by these high temperatures. Experimental results show that the proposed thermal-floorplanning moves based on whitespace utilization, coupled with a method of quickly evaluatingtemperature effects can reduce on chip-temperatures on average by 7K with only a modest 4.2% increase in wirelength and 1.12x increase in execution time. In addition, a method for co-optimizing floorplanning and C4 bump placement using a quadratic optimization process is shown to increase the lifetime of bumps from thermal-cyclic fatigue by 47x with only a modest 3% increase in HPWL wirelength. To combat bump electromigration, a single-bump redundancy technique based on Integer Linear Programming (ILP) is proposed, and shown to be able to reduce the number of redundant bumps to guarantee single-bump redundancy
    by 68% as compared to a naive bump placement approach. Finally, an algorithm to
    redistribute decoupling capacitance, is shown to be able to reduce interconnect temperatures by 12.5K on average and provide a 1.66x increase in electromigration lifetime.
     
  • Wednesday, October 10, 2012

    Seokjoong Kim's paper on Dynamic Voltage Scaling for SEU-Tolerance in Low Power Memories was one of 4 papers nominated for the "Best Paper Award" at VLSI-SOC. While he was not selected as the best paper, this is still an honor to be nominated out of 35 full length papers.

  • Wednesday, September 19, 2012

    Prof. Guthaus in collaboration with Prof. Ricardo Reis and Dr. Gustavo Wilke have written a survey paper in the ACM Transaction on Design Automation of Electronic Systems on "Revisiting Automated Physical Synthesis of High-Performance Clock Networks." The article will appear in an upcoming issue of TODAES.

  • Monday, August 20, 2012

    The OpenRAM project aims to provide an open-source memory compiler framework for Random-Access Memories (RAMs). Most academic Integrated Circuit (IC) design methodologies are inhibited by the availability of memories since commercially available memory compilers are often black box, not modifiable, and have limited available memory configurations. However, memories are the largest barrier to future scaling and require urgent solutions to lower leakage power consumption, improve reliability in shrinking supply voltages, and incorporate post-CMOS technologies. The OpenRAM compiler will enable research in these areas by providing a completely modifiable, verified, technology independent compiler for single-port and multi-port RAMs and many-port register files. The availability of the OpenRAM will enable research in a variety of IC-related disciplines including: computer architecture and system-on-chip (SOC) design, memory circuit and device research, and computer-aided design (CAD).


    This project is a collaboration between Prof. Matthew Guthaus at UCSC and Prof. James Stine at Oklahoma State University.

  • Sunday, July 1, 2012

    Three papers from the VLSI-DA group were accepted into the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). The papers are:

    • Harmonic Resonant Clocking, Haven Skinner, Xuchu Hu and Matthew Guthaus
    • Dynamic Voltage Scaling for SEU-Tolerance in Low-Power Memories, Seokjoong Kim and Matthew Guthaus
    • A Single-VDD Ultra-Low Energy Sub-threshold FPGA, Rajsaktish Sankaranarayanan and Matthew Guthaus

    Congratulations too all the authors!

  • sigda_logo.png
    Thursday, June 28, 2012

    Prof. Guthaus was recently elected to the Executive Committee of the ACM Special Interest Group on Design Automation (SIGDA). Specifically, he was selected as the Finance Chair and is responsible for the budget that sponsors over a dozen conferences (DACICCAD, etc.), educational activities, and international awards.

  • Wednesday, June 27, 2012

    Prof. Guthaus was interviewed in an article on resonant clocks in IEEE Spectrum. The article discusses the recent AMD and Cyclos semiconductor collaboration. Comments from Prof. Guthaus and Phil Restle, IBM, discuss the important future and potential power savings of resonant clocks.

  • DSC_0016 (1).JPG
    Wednesday, June 27, 2012

    Xuchu and Seokjoong graduated earlier this year and Sheldon expects to graduate during the next academic year. These are the first three PhD students from the VLSI-DA lab. Xuchu is currently employed at Cadence, Seokjoong is employed at Oracle, and Sheldon is on an internship at Intel this summer.

  • Tuesday, June 26, 2012

    Prof. Matthew Guthaus from UCSC and Prof. Baris Taskin from Drexel University have been selected to organize and present a tutorial at the 2012 International Conference on Computer Aided Design (ICCAD) on the newest resonant clocking technologies. This tutorial will cover rotary, distributed inductor-capacitor (LC), and standing wave clocks along with the necessary background to understand them. In addition, they will present an overview of the recent work in the design automation area to synthesize these low-power, high-performance resonant clocks. Finally, an overview of the challenges and opportunities in this emerging area will be covered.

  • Monday, May 7, 2012

    Dr. Seokjoong Kim successfully defended his PhD thesis today. His thesis was on low-power design methodologies for memories considering reliability and fault-tolerance. He proposed techniques for improving robustness to aging effects, soft errors, and hard errors while minimizing the power overhead.

  • Thursday, April 26, 2012

    Seokjoong Kim will be defending his PhD thesis on May 7, 2012 from 9:00am-11:00am PST in E2-280.

    Abstract:

    More than 300 million mobile devices are being used and more than 700,000 devices are being activated every single day [70]. These handheld devices are designed to
    operate with low-power for mobility and the increased number of devices need more computing server machines. For both, energy efficient operation is important. Low-power enables not only long battery time for mobile devices but also energy efficiency to the servers.
    However, reduced noise margin due to low-Vdd and process variation due to nano-scaled
    transistor feature sizes increase the number of errors in mobile and server devices. All devices should be resilient, reliable and low-power, and second, low-power and reliability are
    related.

    This work focuses on reliable, low-power methodologies for SRAM memories.
    As a main contribution, this work is the first to consider SRAM cell optimization for power
    and reliability simultaneously. To guide parametric hard faults, this work considers the
    energy optimality and yield considering redundant spare rows and columns. Also this work
    addresses a method for soft error tolerant low-power memory using architectural technique
    to avoid Multiple Bit Upset (MBU) at low voltages. Then methods using dynamic voltage
    scaling for soft error tolerant low-power memory designs are investigated.

    This thesis results in the improvement of memory power consumption and increases the reliability of memory arrays. Using cell optimization, redundancy utilization, interleaving techniques, and adaptive dynamic voltage scaling, memory reliability is increased and power reduction is improved by 10%-40% depending on the applied method
    and situation without sacrificing error tolerance.

  • Friday, April 20, 2012

    Prof. Guthaus was promoted to Associate Professor with tenure. 

  • Monday, March 12, 2012

    Dr. Xuchu Hu successfully defended her PhD thesis on March 8, 2012. Her thesis was on analyzing and considering inductance in clock distribution networks. In particular, she did work in the area of distributed-LC resonant clock grid synthesis and the synthesis of clock trees for electromagnetic compatibility (EMC). Both of these uses consider on-chip inductance in clock networks.

  • Wednesday, February 22, 2012

    Xuchu Hu will be defending her PhD thesis on March 8, 2012 from 2:30-4:30pm PST in E2-399. 

    Abstract:

     

    With better manufacturing technologies, each generation of processors grows smaller, faster, and consumes more power. As microprocessors are operating at multi-GHz speed, power consumption has become a major concern in modern processor design. Especially in portable devices which are battery operated, low power design becomes extreme important. The on-chip clock distribution network (CDN) consumes in excess of 35% of total chip power and occasionally as much as 70% [61]. Most of this power is due to the dynamic switching of the large number of sequential element clock pins that span the entire chip. Clock distribution using inductance (Resonant clock ) has a potential to reduce the maximum power consumption without degrading the clock network performance. Some previous research works demonstrated power savings by connecting extra inductors to clock network. Compared with clock trees, clock grids are often used in high performance processors which operate at higher frequency and consume more power. Previous resonant works either assume simplified clock network or only consider a small sector of the clock network. Inductance is often used in RF designs. In digital circuits, designers usually try to minimize the inductance effect of long interconnections. So the resonant clock synthesis which is related to both digital and analogy design has not been well studied. In this thesis, a methodology to design low power resonant clock grid is described. The key synthesis procedures involved in resonant clock grid design are discussed. The CDN which has a top-level tree driving a resonant grid shows at least 40% power savings and 53% buffer area reduction while using only 30% of a single metal layer for inductors on average. With more advanced on-chip inductor integration techniques, resonant clock grids hold the potential to save up to 90% of the clock grid power. The automated methods can make these multi-disciplinary clocking techniques practical for use in high-performance ASIC designs. At the end of the thesis, the practical issues of resonant clock will be discussed.

  • Wednesday, February 22, 2012

    Curtis Andrus' paper on Lithography-Aware Layout Compaction has been accepted for publication into the Great Lakes Symposium on VLSI (GLSVLSI) to be held in Salt Lake City, Utah.

  • Friday, February 10, 2012

    Xuchu Hu's paper on "Library Aware Resonant Clock Synthesis (LARCS)" was accepted into the 2012 49th Design Automation Conference (DAC).

  • Monday, February 6, 2012

    Xuchu Hu had a journal article on Distributed LC Resonant Clock Grid Synthesis accepted for publication into the IEEE Transactions on Circuits and Systems (TCAS-I).

  • surfit2012.jpg
    Wednesday, January 25, 2012

    Prof. Guthaus is the new Director of the UCSC Summer Undergraduate Research Fellowship in IT (SURF-IT). SURF-IT is accepting applications for undergraduate researchers for summer 2012. *Must be US Citizen or permanent resident.

  • Monday, December 19, 2011

    The University of California Santa Cruz (UCSC) Summer Undergraduate Research Fellowship in Information Technology (SURF-IT) offers opportunities for both UCSC students and non-UCSC students. SURF-IT provides an intensive and personalized summer program for women, minority, or disadvantaged undergraduates. SURF-IT includes a research experience supervised by a UCSC Baskin School of Engineering faculty member. Scholars also have weekly meetings focused on graduate school preparation, how to present research results, research ethics, as well as field trips to local neighboring Silicon Valley research laboratories, and of course a number of social activities.  SURF-IT is sponsored by the Department of Computer Engineering and the National Science Foundation.

    Scholars receive:

    • Stipend ($4500) and Meals
    • Travel to and from program
    • Housing on one of the nation's most beautiful campuses

    The 9-week research projects are in areas of IT-based Integrative System Design, including Sensor Systems, Assistive and Rehabilitative Systems, and Computer Systems. Applicants indicate their desired areas of research, and we will do our best to match students with their top choices.

    http://surf-it.soe.ucsc.edu

  • Monday, December 5, 2011

    Congratulations to Jeren (Jeff) Samandari-Rad for his paper on "Robust Memory Design: Access Time Variability of SRAM" that was accepted into the International Symposium on Quality Electronic Design (ISQED) 2012.

  • Thursday, December 1, 2011

    Prof. Guthaus along with graduate student Xuchu Hu and Brazilian collaborators Prof. Ricardo Reis, Dr. Gustavo Wilke, and Guilherme Flach had a journal article on High-Performance Clock Mesh Optimization accepted for publication into the ACM Transactions on Design Automation of Electronic Systems (TODAES).

  • rsz_1rsz_group_shot_3.jpg
    Friday, August 12, 2011

    The VLSI-DA SURF-IT summer cohort (Kathryn Dobbins, Edward Sullivan, Ryan Conway, and Benjamin LaCara) are presenting posters at the 2011 Summer Undergraduate Research Symposium on August 12, 2011 from 10am-12pm in the E2 Courtyard. More information on their research and others is available at http://surf-it.soe.ucsc.edu/2011titles.

Pages

News