Dr. Rajsaktish Sankaranarayanan defends his PhD thesis!

Date: 
Monday, March 6, 2017

Reducing Variability in Subthreshold Circuits

Reduced form-factor in portable electronics has made energy-efficiency the primary target. Subthreshold operation is a low-power technique delivering significant energy efficiency. However, circuits in subthreshold are very sensitive to process vari- ation. Utilizing subthreshold operation and leveraging energy efficiency necessitates compensation techniques to mitigate process variation.

This work focuses on subthreshold operation in Field Programmable Gate Arrays (FPGAs) and determines the components influencing circuit energy-efficiency.  Mitigating the impact of threshold voltage variation using body bias technique is stud- ied. Using this, a methodology to mitigate the impact of threshold voltage variation in standard cells is developed. With the support of CAD tools this methodology can be extended to FPGAs.

The specific contributions of this thesis are: design and implementation of a subthreshold FPGA chip using body bias as a compensation mechanism against thresh- old voltage variation. analysis of performance and energy of a subthreshold FPGA using a high-level characterization framework. Using this framework the minimum energy point of the subthreshold FPGA was found to be in deep subthreshold, and a performance window of 30X with a 2X energy range was identified. A design methodology to mitigate threshold voltage variation by delivering optimized and adaptive body bias in circuits with standard cells. Using two algorithms, this methodology produces standby energy savings of upto 21.06% on average and active energy savings of upto 9.62% on average.

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