The VLSI Design and Automation group investigates low-power computer chips, circuits and CAD tools to aid circuit design. Please see the Google Scholar site for our most recent publications.


The OpenRAM project aims to provide a free, open-source memory compiler development framework for Random-Access Memories (RAMs).  It is a joint development project between University of California Santa Cruz and Oklahoma State University to enable memory and computer system research by creating an open-source compiler infrastructure.

16kbyte SRAM in AMI 0.5um 45nm 16kbyte SRAM

(Left: 16kbyte SRAM in AMI 0.5um, Right: 16kbyte SRAM in 45nm Process)

Related papers:

M. R. Guthaus, J. E. Stine, S. Ataei, B. Chen, B. Wu, M. Sarwar, "OpenRAM: An Open-Source Memory Compiler," Proceedings of the 35th International Conference on Computer-Aided Design (ICCAD), 2016

S. Ataei, J. Stine, M. Guthaus, “A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS,” International Conference on Computer Design (ICCD), 2016, pp. 499-506.

E. Ebrahimi, M. Guthaus, J. Renau, “Timing Speculative SRAM”, IEEE In- ternational Symposium on Circuits and Systems (ISCAS), 2017

Current-Mode Clocking

In a high-performance computer system design, the clock network consumes a significant amount of power and causes the most switching noise. High power consumption requires larger batteries while switching noise degrades the accuracy of sensitive sensor measurements in modern Systems-on-Chips. Prof. Matthew Guthaus, faculty in Computer Engineering, and his graduate student Riadul Islam, now a faculty at University of Michigan Dearborn, have developed the concept of a current-mode clock distribution to address these problems. Current-mode clocking senses current flow rather than a traditional voltage swing in clock wires and thereby eliminates most of the noise and power problems in traditional clock distribution schemes. Current-mode clocking simultaneously increases the potential maximum speeds of computer chips for performance improvements. Related papers:

R. Islam, M. R. Guthaus, "HCDN: Hybrid-Mode Clock Distribution Networks", IEEE Transactions on Circuits and Systems I: Regular Papers, 2018.

R. Islam, H. Fahmy, P. Lin, M. R. Guthaus, "DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018.

R. Islam, M. R. Guthaus, “Current-Mode Clock Distribution,” IEEE Inter- national Symposium on Circuits and Systems (ISCAS), 2014, pp. 1203-1206.

R. Islam, H. Fahmy, P.-Y. Lin, M. R. Guthaus, “Differential Current-Mode Clock Distribution,” Midwest Symposium on Circuits and Systems (MWSCAS), 2015, pp. 1-4.

R. Islam, M. R. Guthaus, “Low-Power Clock Distribution Using a Current- Pulsed Clocked Flip-Flop,” IEEE Transactions on Circuits and Systems I (TCAS-I), Volume 62, Issue 4, April 2015, pp. 1156-1164.

R. Islam, M. R. Guthaus, “CMCS: Current-Mode Clock Synthesis,” IEEE Transactions on VLSI (TVLSI), Volume 25, Issue 3, September 2016, pp. 1054-1062.

Resonant and Charge-Recovery Clocking

H. Fahmy, P.-Y. Lin, R. Islam, M. R. Guthaus, “Switched Capacitor Quasi- Adiabatic Clocks,” IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp. 1398-1401.

P.-Y.Lin,H.Fahmy,R.Islam,M.R.Guthaus,“LC Resonant Clock Resource Minimization using Compensation Capacitance,” IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp. 1406-1409.

B. Lacara, P.-Y. Lin, M. R. Guthaus, “Multi-Frequency Resonant Clocks,” IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp. 1402- 1405.

X. Hu, M. R. Guthaus, “Distributed LC Resonant Clock Grid Synthesis,” IEEE Transactions on Circuits and Systems I (TCAS-I), Volume 59, Number 11, November 2012, pp. 2749-2760.

Electromagnetic Interference

D. Gorman, M. R. Guthaus, J. Renau, "Architectural opportunities for novel dynamic EMI shifting (DEMIS)", IEEE/ACM International Symposium on Microarchitecture, 2017.

X. Hu, M.R. Guthaus, "Clock tree optimization for electromagnetic compatibility (EMC)", Asia and South Pacific Design Automation Conference, 2011.


  • The OpenRAM team was invited to publish a paper at the IEEE International Electron Devices Meeting (IEDM) onEnabling Design Technology Co-Optimization of SRAMs through Open-Source Software. Prof. Guthaus will be presenting at the December meeting virtually.

  • Google has provided a generous gift to support the OpenRAM memory compiler. This gift will be used for improved coordination with other open-source projects, improved process support, and other general improvements.

  • Hunter Nichols presented his open-source PUF analysis tool -- Puffery. Prof. Guthaus was on the panel discussing gaps in EDA technology. 

  • Two papers from the group were accepted into the VLSI-SOC to be held in Cuzco, Peru on October 6-9, 2019. The first was accepted as a long, oral presentation on Automated Synthesis of Multi-Port Memories and Control by Hunter Nichols, Michael Grimes, Jennifer Sowash, Jesse Cirimelli-Low and Matthew Guthaus. The second was accepted as a short, poster presentation on Bottom Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization by Bin Wu and Matthew Guthaus.